Optimize ASIC test suites using code-coverage analysisMartin Abrahams, TransEDA Ltd, and Stuart Riches, Texas Instruments LtdPerforming code-coverage analysis of HDL code before synthesis saves time ...

Many developers employ code coverage tools but handle requirements coverage in an ad hoc fashion. This often parallels their system design approach, which often follows informal methodologies, if any.

Back in the day, we'd write some code, compile, execute, see what happened and repeat. That was testing. (Sometimes that's still what testing looks like, for better or worse.) Today, we can do a lot ...

Scan is a structured test approach in which the overall function of an integrated circuit (IC) is broken into smaller structures and tested individually. Every state element (D flip-flop or latch) is ...