IEEE

Integrated single-stage column AFE for CMOS image sensor single slope ADCs

Abstract: The paper presents analog and dual correlated double sampling (CDS) stages employed in single-slope analog-to-digital converters (SS-ADC). The converter front-end comprises a single ...
IEEE

A 0.5µm Pixel 3-layer Stacked CMOS Image Sensor with Deep Contact and In-pixel Cu-Cu ...

Abstract: 64Mp CIS with 0.5um pixels has been developed with three wafer layers (e.g. top-wafer for PDs and TG TRs, mid-wafer for pixel TRs, and bottom-wafer for the analog and logic circuits). The ...